FREAパンフレット（英語）

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Top cell: GaAs etc.Bottom cell: SiMetal nano particle, Pd etc.13P.6P.8P.10P.14P.16Hydrogen Energy Carrier TeamWind Power TeamPhotovoltaic Power TeamGeothermal Energy TeamShallow Geothermal and Hydrogeology TeamEnergy Network TeamP.6P.8P.10Hydrogen EnergyCarrier TeamWind Power TeamEnergy Network TeamP.14P.16Geothermal Energy TeamShallowGeothermal andHydrogeologyTeamMajor AchievementsPhosphorus diusion layer formed by ion implantationCrystalline silicon cell fabricated by standard FREA processMain Research Facilities●Next-generation multi-junction solar cell “smart stack technology”The “smart stack technology” using metal nanoparticle arrays has been developed, making the interconnection of various solar cells with dierent materials and bandgaps possible for the rst time. This provides exibility in material choice and device design because the mismatch in lattice constants, thermal expansion coecients, etc. can be disregarded with this technique.A GaAs/InP-based four-junction solar cell has achieved conversion eciency as high as 31.6%, and a GaAs/CIGS-based three-junction solar cell has achieved conversion eciency as high as 24.2% (joint research with the Research Center for Photovoltaics at AIST Tsukuba Center). We are working to improve and establish this technology for mass produc-tion.The use of thin crystalline silicon as a bottom cell provides high eciency and low-cost multi-junction cells. The team is developing crystalline silicon based smart stack cells that go beyond the theoretical eciency limit of single-junction crystalline silicon solar cells (29%). A demonstration GaAs/Si three-junction cell with conversion eciency of 24.7% has been successfully fabricated.1) The standard FREA process for the fabrication of Al‒BSF type crystalline Si cells was established with an average eciency of about 19.3%, equivalent to the highest eciencies reported by companies.2) The technology for thin wafer (0.12 mm thick) slicing from silicon ingots has been established using diamond wires. Processing conditions close to the mass production of a wafer with a thickness of 0.12 mm have been established with a 99.8% yield.3) The smart stack technology was applied to a GaAs/Si-based three-junction cell to achieve conversion eciency as high as 24.7%.4) Industrializable fabrication processes for PERC-type cells and bifacial-type cells were established with eciencies of 20.5% and 20%, respectively.5) A diusion layer with a uniform depth on pyramid-shaped surfaces has been successfully formed by means of ion implantation, demonstrating cell eciency as high as 19.4%.6) New cell and module evaluation techniques (absolute EL method and internal quantum eciency mapping method) were developed. The absolute EL method can be used to visualize energy losses in smart stack cells.Smart stack technologyGaAs/Si-based three-junction smart stack cellElectrode ring furnaceSpin etching apparatusIon implantation equipmentFurnace for forming contacts between the electrode and the diusion layer as well as Al‒BSF layers.Equipment that implants accelerated phosphorus or boron ions in the wafer. The diusion prole can be precisely controlled.Apparatus that etches a single side of the wafer by spin rotation. Only one side can be etched without a protective lm.2μm